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[VHDL-FPGA-Verilog] tpc_vhd

Description: 完整的TPC编译码VHDL程序，直接就可以运行-TPC encoder and decoder
Platform: | Size: 95232 | Author: wanmg | Hits:

[Software Engineering] mpeg

Description: mpeg encoder and decoder
Platform: | Size: 19456 | Author: sk | Hits:

[VHDL-FPGA-Verilog] RS

Description: reed selemon encoder vhdl code
Platform: | Size: 77824 | Author: mohamed saad | Hits:

[Picture Viewer] JPEG

Description: Here is a quite detailed low level design document for the Core: Low Level Design Document for JPEG Encoder
Platform: | Size: 795648 | Author: mahmoud | Hits:

[VHDL-FPGA-Verilog] vhdl

Description: Very high speed integrated Hardware Description Language (VHDL) -是IEEE,工业标准硬件描述语言 -用语言的方式而非图形等方式描述硬件电路 容易修改 容易保存 -特别适合于设计的电路有: 复杂组合逻辑电路,如: -译码器,编码器,加减法器,多路选择器,地址译码 -Very high speed integrated Hardware Description Language (VHDL)- is the IEEE, industry-standard hardware description language- rather than using language to describe graphics hardware, such as easy to modify the circuit easier to save- is particularly suited to the design of the circuit are: the complexity of combinational logic circuits, such as:- Decoder, encoder, plus or minus objects, MUX, address decoding
Platform: | Size: 1735680 | Author: sherry | Hits:

[Communication] RS_Encoder

Description: its a reed solomon encoder-its a reed solomon encoder.....
Platform: | Size: 123904 | Author: haroon | Hits:

[Windows Develop] ABS_17_BIT_SOURCE_CODE

Description: 多摩川绝对值编码器的NRG协议源代码,我们公司用的，我修改的解码程序-Tamagawa NRG absolute encoder protocol source code, used by our company, I modified decoding process
Platform: | Size: 11264 | Author: 王中超 | Hits:

[VHDL-FPGA-Verilog] EnDatlightversion

Description: 海德汉绝对值编码器的ENDAT2.2协议代码，用于编码器数据的解码，然后把得到的数据传送给DSP处理，我们公司用于高精度伺服驱动器上。-Heidenhain encoder absolute agreement ENDAT2.2 code encoder data for decoding the data and then transmitted to the DSP processing, our company for high-precision servo drive.
Platform: | Size: 27648 | Author: 王中超 | Hits:

[MultiLanguage] Pipelined_Implementation_of_Baseline_JPEG_Encoder

Description: Pipelined Implementation of Baseline JPEG Encoder
Platform: | Size: 974848 | Author: BinhTran | Hits:

[MultiLanguage] JPEG_Hardware_Compressor_Encoder

Description: JPEG Hardware Compressor Encoder-JPEG Hardware Compressor Encoder
Platform: | Size: 1480704 | Author: BinhTran | Hits:

[Software Engineering] FPGA-basedincrementalphotoelectricencodercountcirc

Description: 基于FPGA的增量式光电编码器计数电路设计,文章含有Verileg HDL代码.-FPGA-based incremental photoelectric encoder count circuit design, the article contains Verileg HDL code.
Platform: | Size: 231424 | Author: Jiang Guangxiu | Hits:

[VHDL-FPGA-Verilog] chengxu

Description: 一个分频器，一个卷积编码器的程序，都是VDHL的-A frequency divider, a convolutional encoder program, are VDHL of
Platform: | Size: 1024 | Author: chencong | Hits:

[VHDL-FPGA-Verilog] chap9

Description: 用assign 语句描述的三态门，三态双向驱动器，3-8 译码器，8-3 优先编码器-With the assign statement describing the three-state gate, three-state bi-directional drive, 3-8 decoder ,8-3 priority encoder, etc.
Platform: | Size: 7168 | Author: chencong | Hits:

[VHDL-FPGA-Verilog] Manchester

Description: 曼彻斯特编解码源代码,还包含曼彻斯特码的说明文档-Manchester Encoder-Decoder
Platform: | Size: 40960 | Author: cst008 | Hits:

[Multimedia program] PCM

Description: 采用13折线A率的PCM编码,逐次反馈型编码器。-A broken line 13 the rate of use of PCM encoding, successive feedback encoder.
Platform: | Size: 655360 | Author: 军 | Hits:

[VHDL-FPGA-Verilog] Convolutionalencoder

Description: 应用VHDL语言实现的卷积编码器的应用程序-Application of VHDL language implementation of the convolutional encoder applications
Platform: | Size: 7168 | Author: zxy | Hits:

[Communication] conv_vhdl

Description: 用Verilog实现卷积码（2，1，2）的编码器，采用状态机来完成在modelsim下的仿真-Verilog implementation using convolution code (2,1,2) encoder, using a state machine to complete the modelsim simulation under the
Platform: | Size: 1024 | Author: 吴雪 | Hits:

[VHDL-FPGA-Verilog] MAC_MP3_Hardware

Description: MPeg audio encoder/decoder codes
Platform: | Size: 4528128 | Author: prass | Hits:

[VHDL-FPGA-Verilog] motor3_and_motor4

Description: 程序是CPLD双计数器的程序，主要用于电机编码器计数-Program is CPLD pairs of counter procedures, mainly for motor encoder counts
Platform: | Size: 865280 | Author: 王川 | Hits:

[VHDL-FPGA-Verilog] encode

Description: 实现轴编码器的程序，对控制是比较有用的哦-Shaft encoder to achieve the procedure, control is more useful oh
Platform: | Size: 909312 | Author: dongbin | Hits:
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